Package-on-Package (POP) stacking of semiconductor devices is known in the arts. Stacking packages offers significant advantages primarily related to reducing device footprints. It can also be used to improve testability, for example by permitting separate testing of logic and memory packages before they are assembled in a stacked POP unit. In some instances, electrical performance may also be improved due to shortened interconnections between associated packages. Conventional POP designs are generally similar to BGA devices. A bottom package has a substrate with a top surface having a more-or-less centrally located encapsulated area containing enclosed circuitry. The encapsulated area is typically bordered by an unencapsulated periphery bearing exposed leads. A top package, configured to correspond to the bottom package leads, is affixed to the bottom package and the leads are connected using solder balls, wirebonds, or a combination thereof such that the circuitry of the top and bottom packages are operable together.
One of the challenges of POP technology lies in minimizing thickness. A particular problem for POP implementation is posed by the inherent conflict between the need to minimize thickness and the need to minimize and withstand warpage. Warpage can lead to some of the most common and debilitating problems encountered by semiconductor assemblies such as the separation of solder joints, fractures, the separation of layers, and open or short circuits caused by the separation of materials, or by the ingress of moisture between separated materials. Thin assemblies, and assemblies with layers that have differing thermal properties, e.g. POP assemblies, are particularly susceptible to warping. Warpage is generally most severe in the non-molded areas of conventional packages, i.e. the edges, and especially the corners.
Due to these and other problems, improved warp-resistant packages, POP assemblies, and methods for their manufacture would be useful and advantageous in the arts.